About Me

I am a Design Verification Engineer at CoMIRA Solutions Inc, working since December 2023. I hold a Bachelor of Engineering in Computer Systems from NED University of Engineering & Technology. My expertise includes computer vision and FPGA development. In my final year project, I designed a Structural Health Monitoring System on FPGA using Verilog for computer vision and FPGA-based inference. Currently, I am working on an Ethernet project, having studied various clauses of the IEEE 802.3 specification, and am actively involved in R&D. I am dedicated to excellence and passionate about making a meaningful impact in the semiconductor industry.

NED University of Engineering & Technology Karachi,Pakistan

Bachelors in Computer Systems Engineering

Cumulative GPA: 3.179/4.

2019 - 2023

Government Degree Science & Commerce College Malir Cantt

Intermediate (Pre-Engineering)

Grade: A-1

2017 - 2019

Work Experience

Design Engineer

CoMira Solutions Inc.(Offshore Design Center)

Dec 2023 – Present

Karachi, Sindh, Pakistan

Trained on combinational, sequential, and FSM logics.
Verified digital system design through UVM.
Developed tests for Ethernet projects, specifically for MAC (Media Access Control) and PCS (Physical Coding Sublayer).
Studied and implemented various clauses of the IEEE 802.3 specification, focusing on MAC and PCS functionalities.
Conducted detailed analysis and verification of MAC and PCS modules to ensure compliance with the IEEE 802.3 standards.

FPGA-accelerated Computer Vision Intern

Neurocomputation Lab, National Center of Artificial Intelligence

Nov 2022 – Present

Karachi, Sindh, Pakistan

Applied Conventional Computer Vision Techniques for Edge Detection.
Deployment of Deep Neural Network (DNN) on PYNQ Board.
Prototyping of Deep Neural Network on FPGA using MATLAB.

-->

Bachelor’s Thesis & Final Year Project (linked)

Design of Structural Health Monitoring System on FPGA

NED, Karachi

Nov 2022 – Aug 2023

Utilized Verilog to implement conventional computer vision techniques for edge detection.
Trained a custom YOLOv7 model using transfer learning techniques specifically tailored to a dataset of cracks.
Utilized PYNQ Z1 board for prototyping a deep neural network for FPGA-based inference.
Acquired a good understanding of Register Transfer Level (RTL) designs using Verilog and VHDL during the course of my final year project .